1. Field of the Invention
This invention relates to analog circuit designs and, more particularly, to a multiplexer circuit whose high speed operation is unaffected by power supply headroom limitations. More specifically, a multiplexer circuit in accordance with the present invention utilizes bootstrapping to provide high speed operation in the presence of low power supply. The multiplexer circuit is also leakage tolerant and provides high voltage isolation without added circuit complexity.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Multiplexers are logic devices that select between two or more inputs to be transferred to an output. In general, multiplexers may be used within substantially any analog circuit or digital logic block that requires selection between two or more signals. For example, a multiplexer may be included within a clocking network for selecting between two or more clock signals, which may be generated outside of the clocking network (e.g., by an external oscillator coupled to the clocking network) or within the clocking network (e.g., by an internal phase shift apparatus, such as a phase lock loop, PLL, or delay lock loop, DLL). As such, the multiplexer may be configured for transferring a selected one of the clocking signals to the clocking network or a downstream circuit component.
In another example, a multiplexer may be configured for selecting between two or more data signals. For instance, a multiplexer included within a memory device may select between two or more bitline voltages generated during a read operation. FIG. 1 is a block diagram illustrating an exemplary memory device 100. As shown in FIG. 1, the memory device may include a memory cell array 110, a column multiplexer 120 and a sense amplifier 130. The memory cell array 110 may include a number of memory cells arranged in rows and columns. Access to the memory cell array is generally provided by connecting a wordline to each row of memory cells (denoted WL[0 . . . M]) and a bitline to each column of memory cells (denoted BL[0 . . . N]).
During read operations, one or more memory cells may be accessed by asserting the appropriate wordline and selecting one of the bitlines. As shown in FIG. 1, column multiplexer 120 may be coupled to each of the bitlines (BL[0 . . . N]). The column multiplexer is configured for generating read currents through select memory cell(s) by passing a relatively small read bias voltage (e.g., about 1 V) onto the selected bitline. For example, a column select signal (one of col_sel [0 . . . N]) may be supplied to column multiplexer 120 for coupling the selected bitline to sense amplifier 130. In doing so, a current path through the column multiplexer and selected memory cell may be established from the power supply voltage (VCC) on the sense amplifier side to a ground potential (VSS) on the memory cell side. The read currents generated there through may be “sensed” or read by sense amplifier 130 before the output of sense amplifier 130 is passed on to downstream circuitry.
Column multiplexers typically include a number of pass devices, each coupled between the sense amplifier and a different one of the bitlines. In some cases, the pass devices must be able to withstand relatively high voltages. For example, non-volatile memory architectures require memory cell contents to be erased before they can be reprogrammed with new data. During program/erase operations, relatively high voltage biases (e.g., around +/−7V) are applied to the bitline(s) of select memory cell(s) from the high voltage page latch circuitry (140). Because the pass devices must tolerate these high voltage biases, they are often implemented with high voltage transistors having thick gate oxides and high threshold voltages (VT).
Pass devices commonly used within column multiplexers are illustrated in FIG. 2. In most cases, a column multiplexer array may be implemented by coupling several of these pass devices in parallel (e.g., one pass device for every bitline in the memory cell array). In some cases, a pass device may include a single high voltage PMOS transistor (200, FIG. 2a) or a single high voltage NMOS transistor (210, FIG. 2b). In other cases, a pass device may include a pair of high voltage PMOS and NMOS transistors coupled in parallel (220, 230, FIG. 2c). During read operations, read currents are generated through select memory cell(s) by supplying a column select signal (e.g., col_sel[0 . . . N] and/or its complement) to the gate terminal(s) of the pass transistor(s) shown in FIGS. 2a-2c. 
However, a problem arises when the pass devices of FIG. 2 are utilized in low voltage applications. For example, current trends within memory architecture design dictate that supply voltages be reduced to conserve power, improve reliability for small geometry devices, etc. In some cases, a power supply voltage of about 1.5V (or less) may be supplied to a low voltage sense amplifier and memory cell array. However, low power supply voltages provide the column multiplexer with very limited headroom, which can make it difficult for conventional column multiplexers to generate sufficient read currents.
For example, and as shown in FIG. 2, conventional column multiplexers include one or more high voltage devices having relatively high threshold voltages (VT). As a result of limited power supply headroom, these high voltage devices have difficulty passing read bias voltages onto the bitlines to generate sufficient read currents. Essentially, the speed across the column multiplexer is degraded due to the high voltage pass devices and power supply headroom limitations. In some cases, the speed across the multiplexer may be improved by increasing the size of the high voltage pass device. However, an increase in size is rarely feasible or desirable due to the on-pitch nature of the column multiplexer.
Therefore, a need remains for an improved multiplexer design that may be used within low power applications. More specifically, a need remains for a multiplexer circuit, whose high-speed operation is unaffected by power supply headroom limitations. Although applicable to many analog circuit designs, a high-speed, leakage tolerant multiplexer circuit may be particularly useful as a column multiplexer in a variety of non-volatile memory architectures where the multiplexer can be turned off during high voltage operations.